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| 4-3 features ? ansi t1.403 and t1.408 performance monitoring and maintenance functions ? operates in conjunction with mitel's t1/esf framer circuits (mt8976/77 and mh89760b) ? d3/d4 (sf), and esf modes of operation ? one and two second timers ? supports bit-oriented and message-oriented data transfer over the facility data link (fdl) ? esf and d3/d4 yellow alarms, alarm indication signal and loss of signal indication ? framing error, crc error and bipolar violation error counters ? alarm interrupts and counter overflow interrupts applications ? t1 line performance data collection ? csu performance monitoring ? isdn primary rate maintenance controller description the mt8926 performance monitoring adjunct circuit (pmac) interworks with mitel's mt8976/77 and mh89760b to provide performance monitoring data, alarms and t1 maintenance features. it meets the performance monitoring and maintenance requirements of ansi t1.403 and t1.408, and also supports channel service unit (csu) requirements. figure 1 - functional block diagram fdli e8ki irq c2i csti0 csti1 csto reset dsti0 dsti1 dsto f0i transmit bom register receive bom register & rai debounce st-bus interface payload & line loopback control snap- shot registers 8 bit crc counter csi timer bsi fsi sei 4 bit se counter 4 bit fe counter 8 bit bpv counter e8k/fdl mux fdl extractor framer, se/fe detector line loopback integrator b8zs recovery, bpv detector ais/los detector 1sec eclk rxb rxa v ss v dd fdlo e8ko ordering information mt8926ae 28 pin plastic dip MT8926AP 28 pin plcc -40 c to 85 c issue 3 july 1993 mt8926 t1 performance monitoring adjunct circuit (pmac) iso-cmos st-bus ? family
4-4 mt8926 figure 2 - pin connections pin description pin # name description 1v ss system ground. 2eclk extracted clock input . a 1.544 mhz clock derived from the received data. this signal is used to clock in the data on pins rxa and rxb . see figure 11 for timing information. 3rxa receive a input . a unipolar active low signal decoded from the received t1 signal. see figure 11 for timing information. 4rxb receive b input. a unipolar active low signal decoded from the received t1 signal. see figure 11 for timing information. 5ic internal connection. must be tied to v ss for normal operation. 6e8ki extracted 8 khz input. a low going pulse on this input is used by the pmac to locate the framing bit in the received signal. the device uses this information to detect errors in the received framing bits. connect to e8ko of the mt8976/77. see figure 12 for timing information. 7e8ko 8 khz clock output. the 8 khz signal input at e8ki is output on this pin when bit 2 (8ken) of the pmac control word is set. the output is pulled high when 8ken is reset. see figure 12 for timing information. 8v ss system ground. 9 csto control st-bus output. the data that enters the pmac on csti0 will exit the device on this pin. data derived by the pmac will be inserted into specific channels of this output stream. see figures 13 and 14 for timing information and figure 5 for channel allocation. 10 csti0 control st-bus input 0. accepts the serial st-bus stream output on csto of the mt8976/77. the data that enters the pmac on this pin exits the device on csto. the contents of specific csti0 channels is replaced by data derived by the pmac. see figures 13 and 14 for timing information and figure 4 for channel allocation. 11 cs ti1 control st-bus input 1. channel 11 of this st-bus input stream is used to control specific features in the device (table 14). channel 7 is used for the transmit bit-oriented message (table 13), and channel 15 is used to control loopback functions (table 4). see figure 13 for timing information and figure 3 for channel allocation. 12 f0i frame pulse input. this input accepts an 8 khz signal, which is used to delineate the st- bus frame boundary. see figure 15 for timing information. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 28 pin plastic dip vss eclk rxa rxb ic e8ki e8ko vss csto csti0 csti1 f0i c2i vss vdd ic dsti1 dsti0 dsto ic vss ic irq 1sec fdlo fldi reset vdd 1 6 5 432 7 8 9 10 11 23 19 20 21 22 24 25 26 27 28 vss eclk rxa rxb dsti1 ic vdd 12 13 14 15 16 17 18 c2i vdd reset fldi fldo vss f0i dsti0 dsto ic vss ic irq 1sec ic e8ki e8ko vss csto csti0 csti1 28 pin plastic j-lead 4-5 mt8926 13 c2i 2.048 mhz clock input. this input accepts a 2.048 mhz clock signal, which is used to clock st-bus control and data streams into and out of the pmac. see figures 13 and 14 for timing information. 14 v ss system ground. 15 v dd supply voltage input (+5 v). 16 reset reset input. must be high for normal operation. when low, the functions of the mt8926 will be suspended. 17 fdli facility data link input. this input accepts a 4 kbit/sec. facility data link transmit signal, which is routed back out transparently on fdlo if message-oriented signal transmission is enabled (i.e., pmac control word bit 0, fdlen, is low). this signal is not clocked into the pmac. if bit-oriented messaging is enabled (fdlen high), data on this input will not be routed to fdlo (see pin 18, fdlo, below). 18 fdlo facility data link output . when bit-oriented messaging is enabled (i.e., pmac control word bit 0, fdlen, is high), data in the transmit bom register will be appended to a 1111 1111 (ff) flag and clocked out of the device at this output. the output timing for this signal is shown in figure 18. when bit-oriented messaging is disabled (fdlen low), data received at the fdli pin is routed back out transparently on this pin (it is not re-timed). see figure 19 for timing information. 19 1sec 1 second output. a one second timing signal derived from the st-bus f0i signal is output on this pin. the output is low for 0.5 seconds and high for 0.5 seconds. it can be used as an interrupt source to generate t1.403 message-oriented performance reports. see figure 16 for timing information. 20 irq interrupt request output. an open drain output that is to be externally connected to v dd through a pull-up resistor. the pmac will pull this pin low to assert an interrupt request. interrupting events and their groupings are described in tables 16 and 17. irq is released by making bit 1 (interrupt acknowledge - inta) of the pmac control word low. once inta is set, all interrupting signals of a particular group must be inactive before the next interrupt of that group can assert irq . see figure 17 for functional timing information. 21 ic internal connection. must be left open for normal operation. 22 v ss system ground. 23 ic internal connection. must be left open for normal operation. 24 dsto data st-bus output. a 2.048 mbit/sec. serial output stream, which contains the 24 pcm or data channels to be transmitted on the t1 trunk. this data stream is multiplexed from either input dsti0 (normal mode) or input dsti1 (payload loopback mode). the selection of either the normal or payload loopback mode is made through the loopback control word. this output should be connected to dsti of the mt8976/ 77. when the loopback control word is set for line loopback code generation, the 24 pcm channels will contain the line loopback activate or deactivate code stream. see figure 14 for timing information. 25 dsti0 data st-bus input 0. a 2.048 mbit/sec. serial input stream, which contains the 24 pcm or data channels to be transmitted on the t1 trunk in normal mode. this input should be connected to the system side output stream. 26 dsti1 data st-bus input 1. a 2.048 mbit/sec. serial input stream, which contains the 24 pcm or data channels to be transmitted on the t1 trunk in payload loopback mode. this input should be connected to dsto of the mt8976/77. 27 ic internal connection. must be tied to v ss for normal operation. 28 v dd supply voltage input (+5 v). pin description (continued) pin # name description 4-6 mt8926 functional description the mt8926 performance monitoring adjunct circuit (pmac) is designed to enable a mt8976/77 based t1 interface to gather performance data and perform maintenance functions as per ansi t1.403 and t1.408. performance data collection includes crc errors, severely errored framing events, frame synchronization-bit errors, line code violations, and controlled slips. maintenance functions include the detection of alarms, sf line loopback code generation and detection, esf payload loopback, as well as the transport of bit-oriented and message- oriented signals over the facility data link (fdl). the control and status data of the mt8926 is transported over spare channels of the existing mt8976/77 st-bus streams. therefore, no new st- bus streams are required to upgrade with the pmac. the pmac has an on-board framer that uses the received signal and extracted 8 khz clock to achieve synchronization. the result of this frame alignment is logically anded with the syn bit of the mt8976/77 csto stream to give fecv (see table 5). this will ensure that the pmac can only declare synchronization after the framer is synchronized. the mt8926 will align to sf or esf framing without user selection. an interrupt (irq output) system is also provided to reduce the requirement to monitor st-bus channels continuously for exception conditions. interrupt sources are divided into group one (g1) for service affecting events and group two (g2) for counter overflows. a timer has been included to allow scheduling of t1.403/408 message-oriented performance reports for transmission over the facility data link. this timer provides a two second output (register accessed) and a one second output pin. two eight bit counters with overflow bits and resets (resets counter and overflow bit) are provided to record line code violations (bpv) and crc errors. the bpv counter will not count b8zs encoding violations. when either overflow bit goes high it will generate a group two (g2) interrupt. two four bit counters are used to record framing error events (fe) and severely errored framing events (se). the fe counter has an overflow indication bit and can be cleared (resets counter and overflow bit) by the user. its overflow bit will generate a group two (g2) interrupt when it goes high. a g2 interrupt will also be issued whenever the se counter is incremented. the alarms that the pmac monitors are alternate sf yellow alarm (i.e., twelfth sf framing bit =1, alrm), esf facility data link yellow alarm (rai), loss of signal (i.e., reception of 128 or more consecutive zeros), and alarm indication signal (ais, blue alarm or all ones alarm). therefore, the mt8926/mt8976/ 77 combination supports a comprehensive alarm package. the pmac alarm registers and counters are updated as the corresponding events occur. once per frame (8000 times a second) the state of these registers and counters is recorded in a set of snap-shot registers. this data in the snap-shot registers is then inserted into the appropriate bit positions of the st- bus status stream csto. fdl bit-oriented messages can be communicated via the pmac transmit and receive bit-oriented message registers. the user gains access to these registers through the st-bus control streams. valid bit-oriented messages consist of a series of figure 3 - csti1 channel allocation versus t1 channels csti1 0-2 pccw 2 3 x 4-6 pccw 2 7 tx bom 8-10 pccw 2 11 pc w 12-14 pccw 2 15 lc w 16-18 pccw 2 19 x 20-22 pccw 2 23 x 24-26 pccw 2 27 x 28-30 pccw 2 31 x t1 1-3 4-6 7-9 10-12 13-15 16-18 19-21 22-24 transmit bit-oriented message register pmac control word loopback control word bit 7 0 function transmitted first transmitted last bit 7 6 function ser fer 5 4 3 2 1 0 crcr bpvr fsel 8ken inta fdlen bit 1 0 function normal bit 0 0 0 1 1 1 0 1 payload loopback line loopback enable code (00001) line loopback disable code (001) pccw = per channel control word 4-7 mt8926 repeat ing 16 bit code w ords of the form : 11111111 0xxxxxx0, where xxxxxx is the message content. the pmac will automatically append the prefix byte 11111111 to t he trans mit message and remov e it from the receive message. it will also indicate the reception of a valid message. when bit-oriented messages are not being transported, message- oriented facility data link signals, assembled by an external hdlc controller (i.e., mt8952), can be passed through the pmac to the mt8976/77 for transmission. the pmac can implement an esf payload loopback by routing the mt8976/77 dsto stream to the mt8976/77 dsti input (see figure 6). the payload loopback is controlled through the loopback control word, channel 15 of csti1 (see figure 3). when the payload loopback is disabled, data entering the pmacs dsti0 pin is transferred to the pmac dsto. dsto of the pmac should be connected to the dsti pin of the mt8976/77 framer. pmac - framer interworking the mt8926 pmac is designed to function with the mt8976/77 t1 framer. figure 9 illustrates a typical application and the connections involved in realizing this interface. both the pmac and framer receive the extracted clock and data from the t1 line interface. this allows the mt8926 to perform b8zs recovery and bpv detection, as well as sf or esf synchronization, framing error detection, facility data link extraction, and line loopback code detection. some of the csti1 channels that are not used to control the mt8976/77 are used to control the pmac, therefore, csti1 will connect to both devices. figure 3 shows the channels of csti1 that carry the mt8976/77 per channel control words, as well as the mt8926 control data. c2i and f0i supply timing references for both devices. the csto stream of the mt8976/77 framer enters the pmac on csti0 (see figure 4). the pmac adds its performance data to form the csto stream of the pmac. figure 5 shows the channels and status bits that the pmac has added to csto. e8ko of the framer will also pass through the pmac, e8ki to e8ko, under control of csti1. it should be noted that the pmac will replace some of the data of mt8976/77 master status words 1 and 2. this is outlined in tables 1 and 2. table1. master status word 1 data substitution table 2. master status word 2 data substitution the mt8926 can be programmed to either pass data through from fdli to fdlo and on to the mt8976/77 input txfdl, or insert bit-oriented messages into the fdl via the transmit bit-oriented message register, channel 7 of csti1. this function is under control of the fdlen bit of the pmac control word. see application section figure 9 for fdl connections. channel 15 of csti1, the loopback control word, is used to control the line loopback code generation and payload loopback functions of the pmac. this is done by internally connecting the mt8926 dsto to either a line loopback enable code generator, a line loopback disable code generator, dsti0 or dsti1. figure 6 illustrates the connections required to support these functions. the dsto of the framer bit mt8976/77 csto mt8926 csto 7 ylalr ylalr 6 mimic mimic 5 err alrm 4 esfylw rai 3 mfsync mfsync 2 bpv los 1 slip slip 0syn syn bit mt8976/77 csto mt8926 csto 7 blalm blalm 6frcnt frcnt 5 xst xst 4 bpvcnt sei 3 bpvcnt fsi 2 crccnt csi 1 crccnt bsi 0 crccnt ais figure 4 - mt8926 csti0 (mt8976/77 csto) channel allocation versus t1 channels csti0 mt8976/77 csto 0-2 pcsw 3 ps w 4-6 pcsw 7 x 8-10 pcsw 11 x 12-14 pcsw 15 ms w1 16-18 pcws 19 x 20-22 pcsw 23 x 24-26 pcsw 27 x 24-26 pcsw 31 ms w2 t1 1-3 4-6 7-9 10-12 13-15 16-18 19-21 22-24 pcsw psw msw = = = per channel status word phase status word master status word 4-8 mt8926 figure 5 - csto channel allocation versus t1 channels csto 0-2 pcsw 3 ps w 4-6 pcsw 7 pm sw 8-10 pcsw 11 crc 12-14 pcsw 15 ms w1 16-18 pcsw 19 ef ec 20-22 pcsw 23 bpv 24-26 pcsw 2 27 rx bom 28-30 pcsw 31 ms w2 t1 1-3 4-6 7-9 10-12 13-15 16-18 19-21 22-24 cyclic redundancy check-6 error counter bit 7-5 4 function not used lldd (001) bit 7 0 function received first lsb pcsw = per channel status word pmac miscellaneous status word master status word 1 errored frame event counter bit 7-4 3-0 function se (msb-lsb) fe (msb-lsb) lled (00001) fecv tmr (2sec) bomv 3 2 1 0 received bit-oriented message register bipolar violation counter master status word 2 bit function 7msb 0 received last bit 7* function ylalr bit 0 function lsb 7msb 6* 5 4 3* 2 1* 0* mimic alrm rai (esf yellow) mfsync los slip syn bit 7* function blalm 6* 5* 4 3 2 1 0 frcnt xst sei fsi csi bsi ais psw = phase status word * mt8976/77 data unaltered by the mt8926 connects to dsti1 of the pmac and to the receive side of the system. this allows the pmac to perform a payload loopback by internally connecting dsti1 to dsto. in normal operation, transmit data will flow from dsti0 to dsto of the pmac to dsti of the mt8976/77. pmac reset the mt8926 functions may be suspended by making the reset input low (reset must be high for normal operation). in the reset state, data entering the pmac on fdli, dsti0 and csti0 will pass through unaltered to fdlo, dsto and csto respectively. e8ko will be high, irq will be high impedance and the 1sec output (and tmr bit) will be low. after the mt8976/77 has acquired frame synchroni- zation and reset returns high, the mt8926 will require two superframes to acquire synchronization and two st-bus frames to align to the st-bus. reset can be used to prevent ds1 interface figure 6 - payload and line loopback operation repeating 001 repeating 00001 st-bus transmit data stream st-bus receive data stream to pmac control 4 to 1 mux csti1 dsto lcw dsti0 dsti1 from system control csti1 dsti dsto txb txa rxa rxb eclk mt8976/77 mt8926 lcw = loopback control word lcw 0 0 0 1 1 0 1 1 function dsti0 to dsto dsti1 to dsto 00001 to dsto (activate) 001 to dsto (deactivate) 4-9 mt8926 table 3. master status word 1 (csto channel 15) table 4 - loopback control word (csti1 channel 15) note: bits 2 to 7 of the loopback control word are not used. bit name description 7-6 ylalr & mimic these bits (yellow alarm indication and mimic) contain information from the mt8976/77 that is unaltered by the mt8926. see master status word 1 of the mt8976/77 data sheet. 5 alrm alarm. this bit will be set if the mt8926 detects a 1 in the f s bit position of the twelfth frame of an sf superframe (alternate yellow alarm indication). alrm will be low when the f s bit is 0. when receiving an esf signal or if bit 3 (fsel) of the pmac control word (csti1 channel 11) is low, the alrm bit will always be low. 4 rai remote alarm indication (also known as esf yellow alarm). this bit is set if an rai code word (repeating hex ff00 pattern) is received on the esf facility data link. this code must be correctly detected in seven out of 10 messages. rai w ill be reset if more than three of 10 messages are in error. when receiving an sf signal, this bit will always be low. 3mfsync this bit (multiframe synchronization) contains information from the mt8976 that is unaltered by the mt8926. see master status word 1 of the mt8976 data sheet. 2 los loss of signal. this bit will go high when the mt8926 detects 128 or more consecutive zeros in the line signal. it will be reset after the device detects a 12.5% ones density (48 ones in two or less frames) in the received signal. 1-0 slip & syn these bits (slip indication and synchronization) contain information from the mt8976/77 that is unaltered by the mt8926. see master status word 1 of the mt8976/77 data sheet. bit 1 bit 0 description 0 0 normal operation. the transmit data applied to dsti0 will pass through the pmac, and be output on dsto. 0 1 payload loopback mode. connect as per figure 6. the received data on dsto of the mt8976/77 is routed through the pmac to the dsti input of the mt8976/77. 1 0 transmit line loopback enable. connect as per figure 6. dsto of the pmac will be internally connected to an sf line loopback enable code generator. that is, a repeating 00001 code is placed in the 24 t1 channels of dsto, so it may be transmitted by the framer. 1 1 transmit line loopback disable. connect as per figure 6. dsto of the pmac will be internally connected to an sf line loopback disable code generator. that is, a repeating 001 code is placed in the 24 t1 channels of dsto, so it may be transmitted by the framer. interrupts from occurring during system initialization. it should be noted that when the mt8926 is acquiring synchronization the crc and bpv counters may record errors. alrm (sf yellow alarm) the mt8926 will recognize the sixth f s bit of an sf superframe as an alternate yellow alarm indicator, if fsel of the pmac control word is high. that is, when this f s bit is high/low, the alrm bit of master status word 1 will be high/low (see table 3). when an esf signal is being received or when fsel is low, alrm will always be low. a low to high transition of the alrm bit will initiate a group one (g1) interrupt. remote alarm indication (rai) the pmac will decode the bit-oriented priority codeword 11111111 00000000 received on the fd l as a remote alarm indication (rai or yellow alarm) signal as per t1.403/408. see the section on 4-10 mt8926 mt8926 fdl message transfer. this 16 bit pattern must be detected in seven out of 10 codewords in order for the rai bit of master status word 1 (csto channel 15 bit 4) to go high (see table 3). if more than three out of 10 codewords are in error, then rai will remain low. a low to high transition of the rai bit will initiate a group one (g1) interrupt. see the section on interrupts for the control of the rai interrupt. loss of signal indication (los) the los bit of master status word 1, table 3, will be high if the mt8926 receives 128 or more consecutive zeros from the t1 interface. los will return low when a ones density of 12.5% has been achieved (approximately 48 ones is received in two or less frames). payload loopback the payload of a t1 signal consists of the 192 data bits of each frame and excludes the framing bit (the first bit of 193). therefore, a t1.403 or t1.408 esf payload loopback extracts the payload of a receive t1 signal and transmits it back to the originator with new framing bits. this allows the transport of maintenance and performance data over the facility data link while the payload loopback is activated. the crc-6 multiframe alignment remainder will not be looped around, but will function normally (i.e., calculated for each direction of transmission). ) table 5. pmac miscellaneous status word (csto channel 7) bit name description 7-5 --- not used. 4 lldd line loopback disable detect. this bit is set when a repeating 001 pattern (either framed or unframed) is detected in the received t1 signal for at least five frames. in order to comply with t1.403, the user's operating system will ensure that this code is present for at least five seconds before deactivating the sf line loopback (mt8976/77 remote loopback). the mt8926 will detect this repeating bit pattern even in the presence of a ber of 3 errors in 1000 bits. 3 lled line loopback enable detect. this bit is set when a repeating 00001 pattern (either framed or unframed) is detected in the received t1 signal for at least five frames. in order to comply with t1.403, the user's operating system will ensure that this code is present for at least five seconds before activating the sf line loopback (mt8976/77 remote loopback). the mt8926 will detect this repeating bit pattern even in the presence of a ber of 3 errors in 1000 bits. 2 fecv framing error count validation. this bit is set when the mt8926 has synchronized to a framed t1 signal. the framing error count is frozen if this bit is not set. synchronization (fecv=1) is reported when the mt8926 detects two consecutive superframes with correct framing bi ts, and bit 0 in csti0 channel 15 (syn ) is zero. when receiving an sf signal, both f s and f t bits are examined if bit 3 (fsel) in the pmac control word is set. in this case the sixth f s bit is not examined when checking for framing bits. if bit fsel is reset, then only f t bits are examined. loss of synchronization (fecv=0) is reported when either two out of four errors have been detected in the received framing bit position (sf f t bits or esf fps bits) or if bit 0 in csti0 channel 15 (syn ) is set indicating the mt8976/77 has lost synchronization. 1 tmr two second timer. this bit changes state once per second. 0 bomv bit-oriented message validation. this bit will be set when a valid bit-oriented message is present in the receive bom register (table 12, csto, channel 27). it is reset when a valid message is not being received. a valid bit-oriented message has the form 111111110x xxxxx0, wh ere xxxxxx contains the message information. 4-11 mt8926 the mt8926 pmac can perform a payload loopback by muxing the data received on the mt8976/77s dsto to dsti of the mt8976/77. this is controlled by the mt8926 loopback control word (csti1 channel 15, see table 4). figure 6 illustrates the mt8926 payload loopback connections. the st-bus transmit stream (normally connected to dsti of the mt8976/77) will connect to dsti0 of the mt8926. the dsto stream of the mt8976/77 will connect to dsti1 of the mt8926 and to the st-bus receive stream. dsto of the mt8926 will connect to dsti of the mt8976/77. line loopback codes t1.403 defines sf mode line loopback activate and deactivate codes. these codes are either a framed or un-framed repeating bit sequence of 00001 for activation or 001 for deactivation. the standard goes on to say that these codes will persist for five seconds or more before the loopback action is taken. the mt8926 will generate line loopback activate and de-activate codes. these functions are controlled by the loopback control word of csti1 channel 15 (see table 4). the connections illustrated in figure 6 must be implemented for this feature to function. the mt8926 will also detect both framed and un- framed line loopback activate and de-activate codes even in the presence of a ber of 3 errors in 1000 bits. see the pmac miscellaneous status word, table 5, csto channel 7 bit 3 line loopback enable detect (lled) and bit 4 line loopback disable detect (lldd). the line loopback of t1.403 is equivalent to the remote loopback function of the mt8976/77 (see mt8976/77 data sheet, master control word 2). therefore, the user will monitor the lled and lldd bits to ensure that they persist for a minimum of five seconds. then the line loopback can be either activated or de-activated using the mt8976/77 remote loopback function. pmac synchronization the mt8926 has its own frame synchronization mechanism, which uses the received signal (rxa and rxb ) and e8ki to achieve sf and esf frame and superframe alignment. further, the pmac monitors the syn bit of the mt8976/77 (csto channel 15 bit 0) and will not declare synchronization until it is clear. when syn is low and the mt8926 framer is properly aligned for two superframes, the pmac will declare synchronization by making the frame error count validation bit (fecv) high. if this criteria is not met, fecv will be low. the pmac will use the received f t and f s bits, f t bits only or fps bits to acquire synchronization. the receive f t or fps bits are used to determine the out- of-synchronization state (see table 5). timer outputs the pmac has two timer outputs, 1sec pin and csto tmr bit, which are derived from the 8 khz st- bus frame pulse f0i . these signals have been implemented to provide the interface controller with a timing reference for the transmission of t1.403/408 message-oriented performance data over the fdl. see the application section for an explanation of t1.403/408 fdl message transfer. the 1sec output (pin 19) changes state once every half second, and therefore, has a period of one second. the relationship between the 1sec output and the frame pulse f0i is shown in figure 16. tmr is bit one of the pmac miscellaneous status word (csto channel 7, see table 5). it changes state once per second on the rising edge of the 1sec output, and thus, has a two second period. therefore, tmr will change state 62 c2i clock cycles (or st-bus bit times) after the frame pulse that immediately precedes the rising edge of the 1sec output. framing error event counters the mt8926 has two four bit counters, the framing error counter (fe) and the severely errored framing event counter (se). the fe counter will be incremented each time a single framing error in the t1 signal is received. the se counter will be incremented by the reception of a t1 framing pattern with an error rate that is greater than or equal to two out of six bits. see table 8 for errored frame event counter details. table 6. d3/d4 or sf frame pattern table 6 illustrates the terminal framing bits (f t ) and signalling framing bits (f s ) of the sf or d3/d4 frame # f t f s 11 20 30 40 51 61 70 81 91 10 1 11 0 12 0 4-12 mt8926 s table 7. framing bits which affect the se and fe counters framing pattern. refer to table 18 for the esf framing pattern. table 7 illustrates which framing bits are included in the framing error calculations in sf and esf modes with the framing pattern selection bit (fsel), csti1 channel 11 bit 3, high and low. bits marked "1" or "0" are counted, bits marked "x" are excluded. when an sf signal is being received and fsel is low the counters are incremented by f t framing bit error events. fsel must be high for the extended superframe fps bits or both sf f t and f s bits to be included. it should be noted that the twelfth sf framing bit (the sixth f s framing bit) is excluded because it can be used as an sf alternate yellow alarm. the alrm bit of the master status word 1 (csto channel 15 bit 5) will be high if the received alternate yellow alarm bit is high. the alrm bit will always be low if fsel is low. the fe and se counters will wrap around to 0000 after reaching a terminal count of 1111. when the fe framing select sf (f t ) sf (f s ) esf (fps) fsel=0 101010 xxxxxx xxxxxx fsel=1 101010 00111x 001011 counter wraps around the framing error saturation indication bit (fsi) will be set, table 11, and a g2 interrupt will be asserted. the severely errored framing event indication bit (sei), table 11, will be set when the se counter is incremented. this will also assert a g2 interrupt. these counters are frozen when the pmac or mt8976/77 has lost synchronization (i.e., csto channel 7 bit 2, fecv = 0). the se and fe counters, as well as the sei and fsi bits are cleared by a high-to-low transition of bit 7, se counter reset (ser), and bit 6, fe counter reset (fer), of the pmac control word channel 11 csti1. bpv and crc-6 error counters the mt8926 has two eight bit counters, the bipolar violation counter (bpv), table 10, and the crc-6 framing error counter (crc), table 9. the bpv counter is incremented each time a non-b8zs bipolar code violation is received on the t1 interface. the pmac performs b8zs recovery of the receive data before bpvs are detected. the crc-6 framing error counter is incremented when the least significant bit of the mt8976/77 crc error counter is incremented. the bpv and crc counters will wrap around to 00000000 after reaching a terminal count of table 8. framing error and severely errored framing event counters (csto channel 19) bit name description 7-4 se severely errored framing event. this four bit counter is incremented when the mt8926 detects two out of six framing bit errors. it will wrap around after reaching terminal count and can be reset by toggling bit 7 of the pmac control word (table 14, csti1 channel 11) from high to low. when receiving a sf t1 signal, both f s and f t bit errors are counted if bit 3 in the pmac control word is set high. if this bit is set low, only errors in the f t bits will be counted. when both f s and f t bit errors are counted, f s bit 6 (in the twelfth frame in an sf superframe) is not examined for errors because it can be used to indicate a yellow alarm. 3-0 fe framing error count. this four bit counter is incremented when a framing bit error is detected. when receiving a sf t1 signal, both f s and f t bit errors are counted if bit 3 in the pmac control word is set high. if this bit is set low, only errors in the f t bits will be counted. when both f s and f t bit errors are counted, f s bit 6 (in the twelfth frame in an sf superframe) is not examined for errors because it can be used to indicate a yellow alarm. the counter shall wrap around after reaching terminal count and can be reset by toggling bit 6 in the pmac control word (table 14, csti1 channel 11) from high to low. 4-13 mt8926 table 9. crc-6 error counter (csto channel 11) table 10. bipolar violation counter (csto channel 23) table 11. master status word 2 (csto channel 31) bit name description 7-0 crc crc error counter. this is an 8 bit counter, which is incremented when the lsb of the mt8976/77 crc counter toggles. the crc error counter will wrap around after reaching terminal count (i.e., 11111111 to 00000000). this will also set bit 2 (csi) of master status word 2. crc is reset when bit 5 in the pmac control word is toggled from high to low. this counter is invalid when a sf mode t1 signal is being received. bit name description 7-0 bpv bipolar violation counter. this is an 8 bit counter, which is incremented when a line code violation is detected by the mt8926. the counter will wrap around upon reaching terminal count (11111111 to 00000000). this will also set bit 1 (bsi) of master status word 2. bpv is reset when bit 4 in the pmac control word is toggled from high to low. bit name description 7-5 blalm, frcnt & xst these bits (blue alarm, frame count and external status) contain information from the mt8976/77 that is unaltered by the mt8926. see master status word 2 of the mt8976/77 data sheet. 4 sei severely errored framing event indication. this bit goes high when the se counter is incremented (i.e., when the lsb of the se counter toggles). it goes low when bit 7 (ser) of the pmac control word (table 14, csti1 channel 11) is changed from high to low. it can also be cleared by a low on the inta bit of the pmac control word and will remain clear as long as the inta bit is low. 3 fsi framing error counter saturation indication. this bit is set when the fe counter overflows its terminal count (i.e., 1111 to 0000). it will be reset low when bit 6 (fer) of the pmac control word (table 14, csti1 channel 11) is changed from high to low. 2 csi crc error counter saturation indication. this bit is set when the crc counter overflows its terminal count (i.e., 11111111 to 00000000). it will be reset when bit 5 (crcr) of the pmac control word (table 14, csti1 channel 11) is changed from high to low. valid for esf only. 1 bsi bipolar violation counter saturation indication. this bit is set when the bpv counter overflows its terminal count (11111111 to 00000000). it will be reset when bit 4 (bpvr) of the pmac control word (table 14, csti1 channel 11) is changed from high to low. 0 ais alarm indication signal. this bit is set when the mt8976/77 has lost synchronization and less than three zeros are detected in any 250 microsecond interval. it is reset when three or more zeros are detected in a 250 microsecond interval or when synchronization is regained. 11111111. when the b pv count er wraps around the bpv saturation indication bit (bsi) will be set, table 11, and a g2 interrupt will be asserted. similarly, when the crc counter wraps around the crc saturation indication bit (csi) will be set and a g2 interrupt will be asserted. the bpv and crc counters, as well as the bsi and csi bits, are cleared by a high-to-low transition of bit 4, bpv counter reset (bpvr), and bit 5, crc counter reset (crcr), of the pmac control word channel 11 csti1, table 14. 4-14 mt8926 table 12. receive bit-oriented message register (csto channel 27) table 13. transmit bit-oriented message register (csti1 channel 7) bit name description 7-0 rxbom received bit-oriented message. this register contains the eight least significant bits of the esf bit oriented message codeword. the contents of this register is valid when a bit-oriented message codeword is received by the mt8926 in the facility data link bit positions of consecutive extended superframes. a valid codeword will have the form 111111110xxxxxx0. the most significant eight bits (ff sequence) are received first. the register will contain the eight bits following the 11111111 sequence, which are 0xx xxxx0. when a valid codeword is detected, bit zero of the pmac miscellaneous status register is set. bit name description 7-0 txbom transmit bit-oriented message. the contents of this register will be appended to an ff flag to form a bit-oriented codeword, and clocked out on fdlo when bit zero in the pmac control word is set high. the mt8926 will continue to clock this message out until bit 0 in the control word is reset. the order of transmission is bit 7 first. bits 7 and 0 should be zero for a code word to be valid. alarm indication signal (ais) an ais or blue alarm is an all ones signal that can be transmitted from the network side to the terminal equipment side of an interface or from the terminal equipment side to the network side of an interface. in the first case, it indicates that the t1 signal from the network may be lost, and the timing that the terminal equipment derives from the received ais may not be from the network. in the second case, it indicates that data from the terminal equipment side of an interface has been lost and ais is being transmitted in its place. the mt8926 will detect an ais alarm and indicate its presence by making the ais bit of master status word 2 (table 11, csto channel 31 bit 0) high. this state occurs when the mt8976/77 has lost synchronization and less than three zeros are detected in any 250 microsecond interval. the ais bit will go low when either of these conditions is no longer true. mt8926 fdl message transfer the mt8926 will support the transfer of fdl bit- oriented messages in a format that is consistent with t1.403 and t1.408. a bom is transmitted by loading the message into the pmac transmit bit-oriented message register (txbom), table 13, csti1 channel 7. this data has the form 0xxxxxx0, where xxxxxx is the content of the t1.403/408 message. when fdlen (bit zero of the pmac control word, table 14) is made high, the bom is transmitted on the fd l preceded by 11111111. t he start of the bit-oriented message is not synchronous with fdlen going high. therefore, to ensure a message is sent a minimum of n times, the message must be transmitted for 32n + 32 st-bus frames. valid codewords that are received on the fdl are loaded into the receive bit-oriented message register (rxbom, see table 12). a codeword is valid if it f it s the 11111111 0xx xxx x0 form , however, only the 0xxxxxx0 portion of the message will appear in the rxbom register. when a valid codeword has been received the bomv bit of the pmac miscellaneous status word (table 5, csto channel 7 bit 0) will be high. if the next received codeword is not valid, the bomv bit will become zero and the rxbom register will retain its most recent valid message. the mt8926 will support lapd message-oriented performance reporting when it is combined with an hdlc controller such as the mt8952. see figure 7 for fdl operation. the performance monitoring data that makes up the lapd message is derived by the combination of mt8976/77 t1 framer and mt8926 pmac, and is available on csto. this data can then be assembled into a lapd message and presented to the mt8952 hdlc controller for transmission over the fdl on a one second basis as per t1.403/408 (see figure 10). fdlen of the pmac control word (csti1 channel 11 bit 0) must be low to allow transmission of a performance report from the hdlc controller through pins fdli and fdlo of the 4-15 mt8926 table 14. pmac control word (csti1 channel 11) bit name description 7 ser se counter reset. toggling this bit from high to low will reset the severely errored framing event counter (se counter, csto channel 19 bits 7-4) and event indicator (sei bit, csto channel 31 bit 4). 6 fer fe counter reset. toggling this bit from high to low will reset the framing error counter (fe counter, csto channel 19 bits 3-0) and saturation indicator (fei bit, csto channel 31 bit 3). 5 crcr crc counter reset. toggling this bit from high to low will reset the eight bit crc error counter (crc, csto channel 11) and saturation indicator (csi bit, csto channel 31 bit 2) 4 bpvr bpv counter reset. toggling this bit from high to low will reset the eight bit bpv counter (bpv, csto channel 23) and saturation indicator (bsi bit, csto channel 31 bit 1). 3 fsel framing pattern select. with fsel = 1 and an sf signal detected, both f s and f t errors are considered by the fe and se counters. the user must set this bit high in esf mode. with fsel = 0 and an sf signal detected, only errors in f t bits are considered by the fe and se counters. 2 8ken 8 khz output enabled. when 8ken = 1, the e8ko output will be enabled. that is, the signal input at e8ki will be output on e8ko. see figure 12 for timing. when 8ken = 0, the e8ko output will be high. 1 inta interrupt acknowledge. when inta = 1 the mt8926 interrupts are armed or have been triggered (see table 15). once inta is set all interrupting signals of a group must be inactive before another interrupt of that group can assert the irq output (active low). see pin description, pin 20. when this bit is low the irq output state will be high impedance. irq will remain in this state as long as inta remains low or there are no interrupting events (tables 16 and 17). 0 fdlen facility data link enable. fdlen = 1 enables transmission of the facility data link bit- oriented messages on fdlo. the bom byte is stored in the txbom register (table 13, csti1 channel 7). see figure 7 for illustration. when fdlen = 0, the data received on fdli is multiplexed back out of the mt8926 on fdlo. see figure 19 for timing. mt8926 to the txfdl input of the mt8976/77. the 1sec output pin or the two second tmr bit of the miscellaneous status word (csto channel 7 bit 0) are derived from the st-bus timing and can be used to initiate the transmission of these messages. when the mt8926 is synchronized to an sf t1 signal, its receive fdl functions are disabled. bomv of the pmac miscellaneous status register and rai of master status word 1 will be zero. 4-16 mt8926 figure 7 - t1.403/408 fdl message transmission csti1 fdlo csti1 txfdl txfdlclk txb txa rxfdl rxfdlclk { to system control cdsto cdsti cki system control csto 1sec to pmac control 0 1 x 1 x 1 x 1 x 1 x 1 x 1 0 1 2 to 1 mux fdlen fdli rxa rxb eclk from system control txbom pcw fdlen = 1 - transmission of a bit-oriented message over the fdl. pcw fdlen = 0 - transmission of an mt8952 (hdlc controller) assembled message-oriented signal over the fdl. mt8952 mt8976/77 mt8926 8 khz control figure 9 illustrates a typical mt8976/77 - mt8926 application. this diagram shows e8ko (an 8 khz output aligned with the received framing bit) of the t1 framer connected to e8ki of the pmac. the pmac uses this signal for frame alignment, therefore, the 8khsel (master control word 1) of the mt8976/77 must be active for the framer - pmac combination to function properly, even if the interface is in master mode. see the mt8976/77 data sheet. figure 8. functional schematic of interrupt mechanism interrupt sources from snap-shot registers inta sei* fsi csi bsi group 2 group 1 rai alrm syn mt8976/77 mt8976/77 slip delayed frame pulse** toggle detector delay r v dd dq r dq dq dq r dq r irq * sei is reset to 0 when inta = 0. ** delayed frame pulse occurs during bit 7 of st-bus channel 1. v dd 4-17 mt8926 in slave or loop-timed operation 8ken of the pmac control word (table 14, csti1 channel 11 bit 2) will be high, which will pass the signal on e8ki through to e8ko. in master mode or if loop-timing is acquired from another interface, 8ken must be low, which will make e8ko high. interrupts the mt8926 interrupts originate from eight sources, which are divided into two groups. group one (g1) contains alrm (sf yellow alarm), rai (esf yellow alarm), slip and syn - all except slip must be cleared by some means external to the mt8926. group two (g2) contains sei, fsi, csi, and bsi - these can be cleared via the mt8926. see tables 16 and 17 for further information. the interrupting mechanism is controlled by the interrupt acknowledge bit (inta) of the pmac control word (table 14). the status of the interrupts is output on irq . this will allow the three valid states described in table 15. . table 15. interrupt states in the cleared state (inta = 0) interrupt sources are ignored and irq will always be high impedance. if the interrupts are not being used, then inta should remain in the cleared state. when the mt8926 is in the armed state and an interrupt occurs, it will go to the triggered state (irq = 0). state inta bit irq output cleared 0 high impedance armed 1 high impedance triggered 1 0 when a g1 interrupt occurs and irq goes low (triggered), no other g1 or g2 interrupts will affect irq . if irq is then cleared and re-armed, only an active g2 interrupt can trigger irq low unless the g1 interrupt has been removed. that is, both the mt8926 interrupt mechanism and the interrupting source of a group must be cleared before a further interrupt of that group can cause irq to go low. the only exception to this is sei, which can be cleared by inta ( see table 11). a pmac interrupting signal is either a low-to-high transition or a change in state (slip), therefore, for irq to go low the mt8926 must be armed before the initiating edge occurs. in the case where all interrupts are quiescent and then an interrupt becomes active, while the mt8926 is in its clear state, irq will remain in a high impedance condition. this is true even if the mt8926 is then put in the armed state and the interrupt persists (see figure 8). it should be noted that when an sf mode t1 signal is being received the mt8926 crc error counter will be incremented once every two superframes (24 frames or 3 msec.). this is because sf mode t1 has no crc bits. therefore, the crc circuitry of the mt8976/77 will compare the calculated crc remainder with the received fs bits, which will result in a mismatch. this will increment the mt8976/77 and mt8926 crc error counters. the mt8926 crc error counter will count to 255 and then overflow to zero, which will cause an interrupt (irq ). therefore, when an sf mode t1 signal is being received an interrupt will be asserted every 256 x 3 msec. = 768 msec. this can be avoided by clearing the crc error counter before it overflows. a change of state of the 1sec output (once every 0.5 seconds) can be used to trigger a high-to-low ? g1 interrupts are cleared when syn , alrm, and rai = 0. ? the syn interrupt indicates that a los or a ais condition may exist. note: and denotes a logical and. table 16. group one (g1) interrupt activation and clearing signal ? to trigger interrupt (irq low) to clear and arm interrupt ( irq high impedance) alrm alrm bit low to high and other g1 interrupts quiescent and irq high impedance. the inta bit of the pmac control word (csti1 channel 11 bit 1) should be made low to clear the interrupt mechanism (irq high impedance). all g1 interrupts must be quiescent and then inta must be made high before a further interrupt can be generated from g1. see mt8976/77 data sheet master status word 1 for information on the slip and syn bits. rai rai bit low to high and other g1 interrupts quiescent and irq high impedance. slip csti0/csto channel 15 bit 1 (slip) changes state and other g1 interrupts quiescent and irq high impedance. syn ? csti0/csto channel 15 bit 0 (syn ) low to high and other g1 interrupts inactive and irq high impedance. 4-18 mt8926 transition of the crcr bit (csti1 channel 11 bit 5, pmac control word). this will ensure the crc error counter never overflows. slip and syn interrupts the mt8976 slip and syn status bits are passed to the pmac via the mt8976/77 csto to pmac csti0 connection. a mt8926 interrupt will be initiated when the slip bit of the framer changes state. this is the only interrupt source that does not have to be cleared before another interrupt of that group can make irq go low. therefore, when irq is returned to a high impedance condition after a slip interrupt and all other g1 interrupts are quiescent, any g1 interrupt can make irq to go low. a low-to-high transition of the mt8976/77 syn bit will initiate a pmac interrupt. this loss of synchronization situation may indicate that a loss of signal condition (los) exists or that an all ones (ais or blue alarm) is being received. therefore, the syn interrupt service routine should check the state of the ais and los bits of csto. ? g2 interrupts are cleared when sei, fsi, csi and bsi = 0. note: and denotes a logical and. table 17. group two (g2) interrupt activation and clearing signal ? to trigger interrupt (irq low) to clear and arm interrupt ( irq high impedance) sei sei bit low to high and other g2 interrupts quiescent and irq high impedance. the inta bit of the pmac control word (csti1 channel 11 bit 1) should be made low to clear the interrupt mechanism (irq high impedance). all g2 interrupts must be clear and inta must be high before a further interrupt can be generated from g2. the sei bit will remain clear as long as the inta bit is low. sei can also be cleared (low) by toggling ser (csti1 channel 11 bit 7) from high to low. fsi is cleared (low) by toggling fer (csti1 channel 11 bit 6) from high to low. csi is cleared (low) by toggling crcr (csti1 channel 11 bit 5) from high to low. valid for esf only. bsi is cleared (low) by toggling bpvr (csti1 channel 11 bit 4) from high to low. fsi fsi bit low to high and other g2 interrupts quiescent and irq high impedance. csi csi bit low to high and other g2 interrupts quiescent and irq high impedance. bsi bsi bit low to high and other g2 interrupts quiescent and irq high impedance. 4-19 mt8926 applications figure 9 illustrates a typical application of a mt8926 pmac. t1 data is transmitted and received using a generic line interface unit (liu). the liu passes the received data and extracted clock to both the mt8926 and mt8976. e8ko (mt8976) is derived from e1.5i by dividing it by 193 and aligning the result with the receive framing. e8ko (mt8976) connects to e8ki (mt8926), and is used by the mt8926 for frame alignment. e8ko (mt8926) is connected to c8kb of the mt8941. in mt8941 normal mode, c8kb is the reference clock for the st- bus and transmit signals (f0, c4 and c2). this 8 khz output can be turned off (output high) at the mt8926 so the mt8941 reference clock can be derived from another interface. the intrinsic jitter (typical 0.07 ui) and jitter attenuation of the mt8941 will meet t1.408 requirements (see mt8941 data sheet). control of the mt8926 is accomplished over the csti1 st-bus stream, which is shared by the mt8926 and mt8976. status data (performance monitoring information) is inserted into the mt8976 csto stream by the mt8926 and is output on its csto stream. this csto stream data is routed through the mt8980 switch, in message mode, to the microprocessor. the microprocessor will assemble the information section of the t1.403/t1.408 message-oriented signal and pass it to the mt8952 hdlc controller for transmission over the facility data link. the mt8952 must be in external timing mode and will be clocked by the rxfdlclk output to the mt8976. the assembly and transmission of the message-oriented signal is under control of the 1sec output of the mt8926. bit-oriented messages are also transmitted and received via mt8980 message mode access to the csti1 and csto streams. the mt8926 will receive bit-oriented messages from the receive t1 line (i.e., rxa and rxb ). both bit-oriented and message- oriented signals are transmitted over the mt8926 fdlo to mt8976 txfdl link. payload loopback is performed by internally connecting dsti1 to dsto of the mt8926 (under control of the csti1 stream), instead of the normal connection of dsti0 to dsto (see figure 6). irq is an open drain interrupt output that will signal the microprocessor when an exception condition occurs (see figure 8). exception conditions are figure 9 - typical t1.403/t1.408 application a a aaaaaaaaaaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aaaaaaaaaaaaaaaaaaaaa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa from other interfaces to/from other interfaces performance monitoring message/ data storage cdsto cdsti cki t1.403/t1.408 message-oriented signal control int0 int1 m p mt8952 mt8926 mt8941 mt8976 4.7k w vdd sti2 sto3 sto7 sti7 c4i f0i sto0 sto1 sti0 sto2 sti1 16.384 mhz osc. c8kb c4b c2o f0b f0i cvb 12.352 mhz osc. to other t1 interfaces line interface unit (liu) rxa rxb e1 5i f0i c2i csti1 e8ko csto txfdl dsti dsto csti0 rxfdl rxfdlclk txfdlclk rxsf txsf xctl c1.5i txa txb rxa rxb eclk f0i c2i csti1 e8ki csti0 fdlo dsto e8ko csto dsti0 dsti1 irq 1sec fdli to other interfaces t1 receive t1 transmit } mt8980 4-20 mt8926 counter overflows and alarms. interrupts are reset via the pmac control word of the csti1 control stream. t1.403/408 fdl message transfer overview ansi standards t1.403 and t1.408 define an esf mode facility data link (fdl), which is used to transport performance information and control signals across a t1 link. the fdl channel is formed from the framing bit position of every second frame, and therefore, has a 4 kbit/sec. bandwidth. see table 18 for the esf framing pattern. table 18. esf frame pattern the following two fdl message formats are defined in t1.403/408: 1) bit-oriented, which are repeated 16 bit patterns or codeword messages, and 2) message-oriented performance reports, which are lapd protocol messages. bit-oriented messages (boms) are preemptive, and therefore, override other fdl communications. each frame # fps fdl crc 1x 2cb1 3x 40 5x 6cb2 7x 80 9x 10 cb3 11 x 12 1 13 x 14 cb4 15 x 16 0 17 x 18 cb5 19 x 20 1 21 x 22 cb6 23 x 24 1 message consists of a 16 bit codeword of the form 11111111 0x xxx xx 0. therefore, there are 64 unique codewords or messages defined by xxxxxx. refer to t1.403 or t1.408 for a list of messages and message restrictions. boms are further divided into priority messages, and command and response messages. priority messages indicate the existence of a service- affecting failure, and are repeated until the condition that caused the message is removed. these boms are transmitted for at least one second, but may be interrupted as often as once per second, for a maximum of 100 msec. this is to accommodate the periodic transmission of message-oriented performance reports. command and response messages are used to perform various functions, which include the following: 1) line and payload loopback control, 2) protection switch control, 3) synchronization control, 4) reserved for network use, and 5) unassigned. each message consists of a 16 bit codeword of the form 11111111 0xx xx xx0, w hich is repeated at least 10 times. the lapd message-oriented performance reports are sent across the fdl once per second using the bit-assigned message structure of figure 10. each report contains performance data for each second of the previous four seconds. when data for the next one second interval t 0+1 is gathered, it will take the place of t 0 data of the last message. the t 0 data will move to the t 0-1 position, the t 0-1 data will move to the t 0-2 position, the t 0-2 data will move to the t 0-3 position, and the data of t 0- 3 will be discarded. refer to t1.403 or t1.408 for a more complete definition of this protocol. user defined operations, administration and maintenance (oa&m), terminal-to-network and terminal-to-terminal communications may also pass over the fdl. 4-21 mt8926 figure 10 - message-oriented performance report structure (from t1.403 and t1.408) flag sapi c/r ea tei ea control g3 lv g4 u1 u2 g5 sl g6 fe se lb g1 r g2 nm ni g3 lv g4 u1 u2 g5 sl g6 fe se lb g1 r g2 nm ni g3 lv g4 u1 u2 g5 sl g6 fe se lb g1 r g2 nm ni g3 lv g4 u1 u2 g5 sl g6 fe se lb g1 r g2 nm ni fcs 1 2 3 4 5 6 7 8 9 10 11 12 13 14 87 6 5 43 2 1 01111110 00111000 or 00111010 00000001 00000011 one-second report t o t o -1 t o -2 t o -3 } } } } address 00111000 00111010 00000001 control 00000011 one-second report fcs variable interpretation sapi = 14, c/r = 0 (ci) ea = 0 sapi = 14 c/r = 1 (carrier) ea = 0 tei = 0, ea = 1 interpretation unacknowledged information transfer interpretation crc error event = 1 1 4-23 mt8926 figure 11 - receive t1 link timing ? timing is over recommended temperature & power supply voltage ranges. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing . figure 12 - 8khz extracted framing signal ac electrical characteristics ? - 8 khz timing (figures 12) parameters sym min typ ? max units test conditions 1 8khz propogation delay t 8pd 20 ns 50 pf load 2 8khz setup time t 8s 45 ns 3 8khz input low t 8il 0.065 78 m s 4 8khz input high t 8ih 47 m s received t1 link bit cells rxa , rxb eclk 2.25v 0.8v 2.25v 0.8v bit cell t rs t rm t ecw t ecw t p1.5 data eclk e8ki e8ko 2.25v 0.8v 2.25v 0.8v 2.4 v 0.4 v channel 2 bit 1 channel 17 bit 2 channel 2 bit 1 t 8s t 8s t 8il t 8ih t 8pd t 8pd 4-24 mt8926 ? timing is over recommended temperature & power supply voltage ranges. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing . note - the pmac is overwriting some of the bits received on csti0, and transmitting the aggregate on csto. line loopback codes are being transmitted on dsto. note - - the st-bus stream being received on csti0 is not being overwritten, but passes through the pmac unaltered. dsti0 and dsti1 are not overwritten, but passes through the pmac unaltered to the dsto output. figure 13 - st-bus timing - csto/dsto altered by pmac figure 14 - st-bus timing - csto/dsto unaltered by pmac ac electrical characteristics ? - 2048 kbit/s st-bus streams (figures 13 and 14) parameters sym min typ ? max units test conditions 1 clock to output delay t cod 125 ns 150 pf load 2 st-bus setup time t sts 15 ns 3 st-bus hold time t sth 50 ns 4 serial output delay - t sod 35 15 40 ns 150 pf load csto 50 pf load csto 150 pf load dsto c2i csto, dsto csti0/1 2.25v 0.8v 2.4v 0.4v 2.25v 0.8v bit cell boundaries t cod t cod t sts t sth dsti0/1, csti0 dsto, csto 2.25v 0.8v 2.4v 0.4v t sod 4-25 mt8926 ? timing is over recommended temperature & power supply voltage ranges. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing . figure 15 - st-bus clock and frame pulse timing ? timing is over recommended temperature & power supply voltage ranges. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing . figure 16 - 1sec timing ac electrical characteristics ? - clock and frame pulse timing (figure 15) parameters sym min typ ? max units test conditions 1 c2i clock period t 2p 400 488 600 ns 2 c2i clock width high or low t 2w 200 244 300 ns 3 frame pulse setup time t fps 50 ns 4 frame pulse width high t fph 50 ns 5 frame pulse width low t fpl 50 ns ac electrical characteristics ? - 1sec output timing (figure 16) parameters sym min typ ? max units test conditions 1 1sec output delay t 1sd 95 ns 150 pf load c2i f0i 2.25v 0.8v 2.25v 0.8v t 2p t 2w t 2w t fps t fph t fpl f0i c2i 1sec 2.25v 0.8v 2.25v 0.8v 2.4v 0.4v t 1sd t 1sd 4-26 mt8926 figure 17 - interrupt functional timing ? timing is over recommended temperature & power supply voltage ranges. ? typical figures are at 25c and are for design aid only; not guaranteed and not subject to production testing . figure 18 - fdl bit-oriented message timing figure 19 - fdl message-oriented signal timing ac electrical characteristics ? - facility data link timing (figures 18 and 19) parameters sym min typ ? max units test conditions 1 data link output delay t dod 45 ns 150 pf load 2 data link propagation delay t dpd 40 ns 150 pf load frame n frame n + 1 csti0/1 c2i irq high z active low high z ch 0 ch 1 ch 11 ch 12 10 7 6 2 1 * 07 6 * * t iod t iod * ** note: inta bit. irq is returned to high z by inta=0, inta=1 in the previous frames. this can occur in frame n+1 or in a later frame. condition initiating interrupt t iod (irq output delay) is dependent on the irq pull-up resistor. ch 11 ch 12 ch 31 ch 0 1* 76 2107654 c2i f0i fdlo 2.4v 0.4v fdli data txbom data t dod *fdlen = 1, fdlen=0 in the previous frames. a a aa aa aa aaa a a aa a a aa a a aa a a aa a a aa a a aa fdli fdlo 2.25v 0.8v 2.4v 0.4v t dpd note: fdlen = 0 4-27 mt8926 appendix control and status register summary master control word 1 (channel 15, csti0) master control word 2 (channel 31, csti0) per channel control words (all channels on csti0 except channels 3, 7, 11, 15, 19, 23, 27 and 31) transmit bit-oriented message register (channel 7, csti1) pmac control word (channel 11, csti1) loopback control word (channel 15, csti1) per channel control words (all channels on csti1 except channels 3, 7, 11, 15, 19, 23, 27 and 31) phase status word (channel 3, csto) 76543210 debounce 1 disabled 0 enabled tspzcs 1 disabled 0 enabled b8zs 1 b8zs 0 jammed bit 8khsel 1 disabled 0 enabled xcti 1 set high 0 cleared esfylw 1 enabled 0 disabled robbed bit 1 disabled 0 enabled ylalr 1 enabled 0 disabled rmloop 1 enabled 0 disabled dgloop 1 enabled 0 disabled all 1s 1 enabled 0 disabled esf/d4 1 esf 0 d3/d4 reframe device reframes on high to low transition slc-96 1 enabled 0 disabled crc/mimic see note 1 maint. 1 4/12 0 2/4 unused - keep at 0 polarity 1 no inversion 0 inversion loop 1 ch. looped back 0 normal data 1 enabled 0 disabled transmitted first txbom transmitted last ser high-to-low reset fer high-to-low reset crcr high-to-low reset bpvr high-to-low reset fsel 1 f s , f t , fps 0 f t only 8ken 1 enabled 0 disabled inta 1 enabled 0 disabled/ clear fdlen 1 txbom-to- fdl 0 fdli-to-fdlo unused 00 normal 01 payload 10 ll enable 11 ll disable unused - keep at 0 a txt. sig. bit b txt. sig. bit c txt. sig. bit d txt. sig. bit channel count bit count 4-28 mt8926 appendix (continued) control and status register summary pmac miscellaneous status word (channel 7, csto) cyclic redundancy check-6 error counter (channel 11, csto) master status word 1 (channel 15, csto) severely errored framing event and error counters (channel 19, csto) bipolar violation error counter (channel 23, csto) receive bit-oriented message register (channel 27, csto) master status word 2 (channel 31, csto) per channel status word (all channels on csto except channels 3, 7, 11, 15, 19, 23, 27, 31) note 1: in esf mode: 1: crc calc. ignored during sync. 0: crc checked for sync. in d3/d4 mode: 1: sync. to first correct s-bit pattern. 0: will not sync. if mimic detected. 765 4 3 2 1 0 unused lldd 1 detected 0not detected lled 1 detected 0not detected fecv 1 in-sync 0 out-of-sync tmr changes state once per second bomv 1 valid 0 invalid crc error count ylalr 1 detected 0normal mimic 1 detected 0not detected alrm 1 detected 0not detected rai 1detected 0not detected mfsync 1 not detected 0 detected los 1 detected 0normal slip changes state when slip performed syn 1 out-of-sync. 0 in-sync severely errored framing event counter (se) fram ing error counter (fe) bpv error count received first rxbom received last blalm 1 detected 0not detected frcnt frame count xst 1xst high 0 xst low sei 1 se toggles 0 ser high- to-low fsi 1 fe f-to-0 0 fef high- to-low csi 1 crc ff- to-00 0 crcr high- to-low bsi 1 bpv ff-to- 00 0 bpvr high- to-low ais 1 detected 0not detected unused a recd. sig. bit b recd. sig. bit c recd. sig. bit d recd. sig. bit |
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